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ISL8201M
? The ground connection between pin 11 and pin 1 to 4
should be a solid ground plane under the module.
? Place a high frequency ceramic capacitor between (1) VIN
and PGND (pin 11) and (2) PVCC and PGND (pin 1 to 4)
as close to the module as possible to minimize high
frequency noise
? Use large copper areas for power path (VIN, PGND,
VOUT) to minimize conduction loss and thermal stress.
Also, use multiple vias to connect the power planes in
different layers.
? Keep the trace connection to the feedback resistor short
? Avoid routing any sensitive signal traces near the PHASE
node
3.5
Thermal Considerations
Experimental power loss curves along with θ JA from thermal
modeling analysis can be used to evaluate the thermal
consideration for the module. The derating curves are
derived from the maximum power allowed while maintaining
the temperature below the maximum junction temperature of
+125°C. In actual application, other heat sources and design
margin should be considered.
12
3.0
2.5
1.5V
3.3V
10
8
2.0
1.5
0.6V
6
3.3 V
1.5 V
0.6 V
4
1.0
0.5
2
0.0 0
2
4
6
8
10
0
60
70
80
90
100
110
LOAD CURRENT (A)
FIGURE 22. POWER LOSS vs LOAD CURRENT (5V IN )
4.0
12
AMBIENT TEMPERATURE (°C)
FIGURE 23. DERATING CURVE (5V IN )
3.5
3.0
2.5
2.5V
3.3V
5.0V
10
8
5.0V
1.5V
0.6V
1.5V
2.0
1.5
1.0
0.5
0.6V
6
4
2
2.5V
3.3V
0.0
0
2
4
6
8
10
0
60
70
80
90
100
110
LOAD CURRENT (A)
FIGURE 24. POWER LOSS vs LOAD CURRENT (12V IN )
13
AMBIENT TEMPERATURE (°C)
FIGURE 25. DERATING CURVE (12V IN )
FN6657.2
October 21, 2010
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